MathWorks Simulink Design Verifier v2.0

MathWorks has announced that Simulink Design Verifier now includes Polyspace analysis technology for automated error detection in Simulink models. Simulink Design Verifier 2.0 integrates Polyspace error detection with existing property proving and test generation capabilities to help reduce the time required to find and fix the root cause of design errors, decreasing the overall cost of verification and validation.

Engineers across the aerospace, automotive, medical and industrial automation and machinery industries can now apply Model-Based Design with formal analysis methods provided by Simulink Design Verifier 2.0 to identify design errors in Simulink and Stateflow models without extensive testing or simulation.

Key product features include detection of dead logic, integer and fixed-point overflows, division by zero and assertion violations; blocks and functions for modelling functional and safety requirements; test vector generation from functional requirements and model coverage objectives; property proving, with generation of violation examples for analysis and debugging; and fixed-point and floating-point model support.